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SiI 164 PanelLink Transmitter Data Sheet
Document # SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Silicon Image, Inc.
SiI-DS-0021-C April 2002
Application Information
To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon Image web site at www.siliconimage.com or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Trademark Acknowledgment
Silicon Image, the Silicon Image logo, PanelLink and the PanelLink Digital logo are registered trademarks of TM (R) TM Silicon Image, Inc. TMDS is a trademark of Silicon Image, Inc. VESA , FPD are trademarks of the Video 2 Electronics Standards Association. I C is a trademark of Philips Semiconductor. All other trademarks are the property of their respective holders.
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Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. All information contained herein is subject to change without notice.
Revision History
Revision SiI-DS-0021-0.1 SiI-DS-0021-0.8 SiI-DS-0021-A SiI-DS-0021-B SiI-DS-0021-C Date 06/99 07/99 01/99 03/99 04/02 Comment First Draft Preliminary Release Full Release Internal Revision B release 2 New format. I C programming and strapping mode description, TFT mapping and Design Recommendations, pin names ISEL/RST changed to ISEL/RST# and PD to PD#.
(c) 2002 Silicon Image, Inc.
SiI-DS-0021-C
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SiI 164 PanelLink Transmitter Data Sheet
TABLE OF CONTENTS
General Description ........................................................................................................................................ 1 Features ...................................................................................................................................................... 1 SiI 164 Pin Diagram........................................................................................................................................ 1 Functional Description .................................................................................................................................... 2 Electrical Specifications .................................................................................................................................. 3 Absolute Maximum Conditions.................................................................................................................... 3 Normal Operating Conditions...................................................................................................................... 3 Digital I/O Specifications ............................................................................................................................. 3 DC Specifications ........................................................................................................................................ 4 AC Specifications ........................................................................................................................................ 5 Input Timing Diagrams ................................................................................................................................ 6 Pin Descriptions .............................................................................................................................................. 8 Input Pins .................................................................................................................................................... 8 Configuration Pins ....................................................................................................................................... 9 Input Voltage Reference Pin...................................................................................................................... 10 Power Management Pins .......................................................................................................................... 10 Differential Signal Data Pins...................................................................................................................... 10 Reserved Pins ........................................................................................................................................... 10 Power and Ground Pins ............................................................................................................................ 10 2 I C Registers..................................................................................................................................................11 2 I C Register Mapping .................................................................................................................................11 2 I C Register Definitions ............................................................................................................................. 12 2 I C Slave Interface and Address ............................................................................................................... 14 Data De-skew Feature .............................................................................................................................. 15 Data Latching Modes ................................................................................................................................ 16 2 I C Programming Sequence ..................................................................................................................... 17 Enabling Hot Plug Detection Mode ........................................................................................................... 17 2 Non I C Mode Configuration ..................................................................................................................... 18 TFT Panel Data Mapping.............................................................................................................................. 20 Design Recommendations............................................................................................................................ 23 2 1.5V to 3.3V I C Bus Level-Shifting........................................................................................................... 23 Voltage Ripple Regulation ......................................................................................................................... 24 Decoupling Capacitors .............................................................................................................................. 25 Series Damping Resistors on Outputs ...................................................................................................... 26 Differential Trace Routing.......................................................................................................................... 26 Package Dimensions .................................................................................................................................... 28 Ordering Information..................................................................................................................................... 28
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SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
LIST OF TABLES
Table 1. Sample Programming Sequence for SiI 164................................................................................... 17 2 Table 2. Non I C Strapping Mode Options .................................................................................................... 19 TM Table 3. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2 Compliant........................... 20 Table 4. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode ................................ 21 Table 5. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode ................................ 22 Table 6. Recommended Components for Bypass and Decoupling Circuits ................................................. 25
LIST OF FIGURES
Figure 1. Pin Diagram for SiI 164 ................................................................................................................... 1 Figure 2. Functional Block Diagram................................................................................................................ 2 Figure 3. Clock Cycle High/Low Times ........................................................................................................... 6 Figure 4. Low Swing Differential Times .......................................................................................................... 6 Figure 5. ISEL/RST# Minimum Timing ........................................................................................................... 6 Figure 6. Input Data Setup/Hold Time to IDCK............................................................................................... 7 Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE....................................................................... 7 Figure 8. DE High and Low Times .................................................................................................................. 7 2 Figure 9. I C Data Valid Delay (driving Read Cycle data) ............................................................................... 7 2 Figure 10. I C Byte Read .............................................................................................................................. 14 2 Figure 11. I C Byte Write .............................................................................................................................. 14 Figure 12. SiI 164 Data De-skew Feature Timing......................................................................................... 15 Figure 13. 12 bit Input Data Latching............................................................................................................ 16 Figure 14. 24 bit Input Data Latching............................................................................................................ 16 2 Figure 15. Non I C Mode Schematic Example ............................................................................................. 18 2 Figure 16. I C Bus Voltage Level-Shifting using Fairchild NDC7002N ......................................................... 23 2 Figure 17. I C Bus Voltage Level Shifting using Philips GTL 2010............................................................... 23 Figure 18. Voltage Regulation using TL431.................................................................................................. 24 Figure 19. Voltage Regulation using LM317 ................................................................................................. 24 Figure 20. Decoupling and Bypass Capacitor Placement ............................................................................ 25 Figure 21. Decoupling and Bypass Schematic ............................................................................................. 25 Figure 22. Series Input Damping Resistors for Driving Source .................................................................... 26 Figure 23. Example of Incorrect Differential Signal Routing ......................................................................... 26 Figure 24. Example of Correct Differential Signal Routing ........................................................................... 27 Figure 25. Differential Trace Routing to DVI Connector(Top Side View) ...................................................... 27 Figure 26. 64-pin TQFP Package Dimensions (JEDEC code MS-026ED) .................................................. 28
SiI-DS-0021-C
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SiI 164 PanelLink Transmitter Data Sheet
April 2002
General Description
The SiI 164 transmitter uses PanelLink(R) Digital technology to support displays ranging from VGA to UXGA resolutions (25 - 165Mpps) in a single link interface. The SiI 164 transmitter has a highly flexible interface with either a 12-bit mode (1/2 pixel per clock edge) or 24-bit mode 1-pixel/clock input for true color (16.7 million) support. In 24-bit mode, the SiI 164 supports single or dual edge clocking. In 12-bit mode, the SII164 supports dual edge single clocking or single edge dual clocking. The SiI 164 can be programmed 2 though an I C interface. In addition the SiI 164 also supports Receiver and Hot Plug Detection. PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost.
Features
* * * * * * * * * * Scaleable Bandwidth: 25 - 165MHz (VGA to UXGA) Flexible Graphics Controller Interface: 12-bit or 24-bit mode 1 pixel/clock inputs Flexible Input Clocking: Single clock single edge (24-bit), Single clock dual edge (12-/24bit), Dual clock single edge (12-bit) 2 I C Slave Programming Interface up to 100kHz Low Voltage Interface: 3.3V with option for 1.0 to 3.0V Low Voltage Signal Mode Monitor Detection supported through hot plug and receiver detection De-skewing Option varies input clock to input data timing Low Power: 3.3V operation (120mA max.) and Power Down mode (1mA max.) Cable Distance Support: over 5m with twisted pair and fiber-optics ready Compliant with DVI 1.0 (DVI is backwards compliant with VESA(R) P&DTM and DFP)
SiI 164 Pin Diagram
EXT_SWING AGND PVCC1 18 AGND AGND AVCC AVCC PGND 17 16 15 14 13 12 11 TXC+ 22 TX2+ TX1+ TX0+ TXC21 TX2TX024 TX127
32
31
30
29
28
26
25
23
20
19
VCC RESERVED DKEN D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 GND
33
GND BSEL/SCL DSEL/SDA ISEL/RST# VCC MSEN PD EDGE/HTPLG CTL1/A1/DK1 CTL2/A2/DK2 CTL3/A3/DK3 VSYNC HSYNC VREF DE VCC
34 35 36 37 38 39 40 41 42 43 44 45 46 47 54 58 62 50 51 52 53 55 56 57 59 60 49 61 63 D0
SiI 164
64-Pin TQFP
(Top View)
10 9 8 7 6 5 4 3 2 64 GND 1
48
PVCC2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
IDCK-
Figure 1. Pin Diagram for SiI 164
IDCK+
D1
1
SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Functional Description
The SiI 164 is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 24 bits for data Input to allow for panel support up to UXGA resolution. Figure 2 shows the functional blocks of the chip.
MSEN
TXC+
TX0+
TX1+
PanelLink Digital core I2C Slave Machine
SDA SCL A[3:1]
TX2+
EXT_SWING
Registers & Configuration Logic Block Data Capture Logic Block
VREF
EDGE/HTPLG DSEL/SDA
ISEL/RST
BSEL/SCL DKEN
HSYNC
VSYNC
IDCK+
PD
DE
CTL/A/DK[3:1]
Figure 2. Functional Block Diagram
SiI-DS-0021-C
2
D[23:0]
IDCK-
SiI 164 PanelLink Transmitter Data Sheet
Electrical Specifications
Absolute Maximum Conditions
Absolute Maximum Conditions are defined as the worst case conditions the part will tolerate without sustaining damage. Permanent device damage may occur if absolute maximum conditions are exceeded. Proper operation under these conditions is not guaranteed. Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Symbol VCC VI VO TJ TSTG Parameter Supply Voltage 3.3V Input Voltage Output Voltage Junction Temperature (with power applied) Storage Temperature Min -0.3 -0.3 -0.3 -65 Typ Max 4.0 VCC+ 0.3 VCC+ 0.3 125 150 Units V V V C C
Normal Operating Conditions
Symbol VCC VCCN TA JA Note 1. Airflow at 0m/s. Parameter Supply Voltage Supply Voltage Noise Ambient Temperature (with power applied) Thermal Resistance (Junction to Ambient)
1
Min 3.0 0
Typ 3.3 25 64
Max 3.6 100 70
Units V mVP-P C C/W
Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol VIH VIL VDDQ VSH VSL VCINL VCIPL IIL VIH
2
Parameter High Swing High-level Input Voltage High Swing Low-level Input Voltage Low Swing Voltage Low Swing High-level Input Voltage Low Swing Low-level Input Voltage 1 Input Clamp Voltage 1 Input Clamp Voltage Input Leakage Current High Swing High-level Input Voltage
Conditions VREF = VCC VREF = VCC
Min 2.0
Typ
Max
Units V V V V V V V A V
0.8 1 VDDQ/2 + 300mV 3.0
VREF = VDDQ/2 VREF = VDDQ/2 ICL = -18mA ICL = 18mA
-10 VREF = VCC 2.0
VDDQ/2 - 100mV GND -0.8 VCC + 0.8 10
Notes 1. Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions 2. VDDQ defines the maximum voltage level of Low Swing input. It is not an actual input voltage. Chip characterization for Low Swing operation is performed at 1.5V only. Voltage level of Low Swing input should never exceed absolute maximum rating.
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SiI 164 PanelLink Transmitter Data Sheet
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol VOD VDOH IDOS IPD# ICCT Parameter Differential Voltage Single ended peak to peak amplitude Differential High-level Output 1 Voltage Differential Output Short Circuit 1 Current 2 Power-down Current Transmitter Supply Current Conditions RLOAD = 50, REXT_SWING = 510 Min 510 Typ 550 AVCC VOUT = 0 V 0.2 85 5 1.0 120 Max 590 Units mV V A mA mA
IDCK= 165 MHz, 1-pixel/clock mode, REXT_SWING = 510, IVCC = VCC, 3 Worst Case Pattern
Notes 1. Guaranteed by design. 2. Assumes all inputs to the transmitter are not toggling. 3. Black and white checkerboard pattern, each checker is one pixel wide.
SiI-DS-0021-C
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SiI 164 PanelLink Transmitter Data Sheet
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol TCIP FCIP TCIH TCIL TIJIT TSIDF Parameter IDCK Period, 1-pixel/clock IDCK Frequency, 1-pixel/clock IDCK High Time at 165MHz IDCK Low Time at 165MHz Worst Case IDCK Clock Jitter Data, DE, VSYNC, HSYNC Setup Time to IDCK falling edge (Default De-skew Setting) Data, DE, VSYNC, HSYNC Hold Time from IDCK falling edge (Default De-skew Setting) Data, DE, VSYNC, HSYNC 1 Setup Time to IDCK rising edge (Default De-skew Setting) Data, DE, VSYNC, HSYNC 1 Hold Time from IDCK rising edge (Default De-skew Setting) Data, DE, VSYNC, HSYNC 1 Setup Time to IDCK falling/rising edge (Default De-skew Setting) Data, DE, VSYNC, HSYNC 1 Hold Time from IDCK falling/rising edge (Default De-skew Setting) VSYNC, HSYNC Delay from DE falling 1 edge 1 VSYNC, HSYNC Delay to DE rising edge DE high time DE low time
1 1 2,3
Conditions
Min 6 25 2.0 2.0
Typ
Max 40 165
Units ns MHz ns ns ns ns
Figure
Figure 3 Figure 3 Figure 3 Figure 6
2 Single Edge (DSEL = 0, EDGE = 0) Single Edge (DSEL = 0, EDGE = 0) Single Edge (DSEL = 0, EDGE = 1) Single Edge (DSEL = 0, EDGE = 1) Dual Edge (DSEL = 1, BSEL = 0) Dual Edge (DSEL = 1, BSEL = 0) 1.0
THIDF
0.9
ns
Figure 6
TSIDR
1.0
ns
Figure 6
THIDR
0.9
ns
Figure 6
TSID
0.6
ns
THID
1.3
ns
TDDF TDDR THDE TLDE TSTEP TRESET TI2CDVD SHLT
1TCIP 1TCIP 8191TCIP 128TCIP DKEN = 1 10 CL = 10pf CL = 400pf RLOAD = 50, REXT_SWING = 510 RLOAD = 50, REXT_SWING = 510 170 200 700 2000 230 260
ns ns ns ns ps s ns ns ps
Figure 7 Figure 7 Figure 8 Figure 8 Figure 5 Figure 9 Figure 4
De-skew step size increment Duration of RESET signal Low required for valid Reset
SDA Data Valid Delay from SCL high 3 to low transition
Differential Swing High-to-Low Transition Time Differential Swing Low-to-High Transition Time
SLHT
170
200
230
ps
Figure 4
Notes 1. Guaranteed by design. 2. Actual jitter tolerance may be higher depending on the frequency of the jitter. 2 2 3. All Standard mode I C (100kHz) timing requirements are guaranteed by design. Fast mode I C (400kHz) timing requirements are guaranteed at 10pf loading.
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SiI 164 PanelLink Transmitter Data Sheet
Input Timing Diagrams
TCIP TCIH 2.0 V 2.0 V 2.0 V
0.8 V TCIL
0.8 V
Figure 3. Clock Cycle High/Low Times
SLHT
SHLT
80% VOD 20% VOD
Figure 4. Low Swing Differential Times
VCC
ISEL/RST# TRESET
Figure 5. ISEL/RST# Minimum Timing
SiI-DS-0021-C
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SiI 164 PanelLink Transmitter Data Sheet
IDCK TSIDF D[23:0], DE, HSYNC,VSYNC 50 %
50 % THIDF
50 %
50 % TSIDR THIDR
Figure 6. Input Data Setup/Hold Time to IDCK
DE
0.8 V TDDF
DE TDDR 0.8 V VSYNC, HSYNC, CTL[3:1] 0.8 V
0.8 V
VSYNC, HSYNC, CTL[3:1]
Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE
THDE DE
2.0 V
2.0 V 0.8 V
0.8 V
TLDE
Figure 8. DE High and Low Times
SDA
TI2I2CDVD
SCL
2
Figure 9. I C Data Valid Delay (driving Read Cycle data)
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SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Pin Descriptions
Input Pins
Pin Name
D[23:12]
Pin # Type Description
36-47 In Top half of 24-bit pixel bus. When BSEL = HIGH, this bus inputs the top half of the 24-bit pixel bus. When BSEL = LOW, these bits are not used to input pixel data. In this mode, the state of D[23:16] is input to the 2 I C register CFG. This allows 8-bits of user configuration data to be read by the graphics 2 2 controller through the I C interface (see I C register definition). When not used D[23:16] should be tied to ground. D[15:12] are reserved for SiI use only and should be tied to GND. Bottom half of 24-bit pixel bus / 12-bit pixel bus input. When BSEL = HIGH, this bus inputs the bottom half of the 24-bit pixel bus. When BSEL = LOW, this bus inputs 1/2 a pixel (12-bits) at every latch edge (both falling and/or rising) of the clock. Input Data Clock +. Input Data Clock -. This clock is only used in 12-bit mode when dual edge clocking is turned off (DSEL = LOW). It is used to provide the ODD latching edges for dual clock single edge. If BSEL = HIGH or DSEL = HIGH, this pin is unused and should be tied to GND. Input Data Enable. This signal qualifies the active data area. DE is always required by the transmitter and must be high during active display time and low during blanking time. Horizontal Sync input control Signal Vertical Sync input control signal. The use of these multi-function inputs depends on the settings of ISEL/RST# and DKEN. These inputs are regular high-swing 3.3V CMOS level inputs. These pins contain weak pulldown resistors so that if left unconnected, they will be LOW. When ISEL/RST# = LOW, DKEN = LOW General Purpose Input CTL[3:1] pins are active, for backward compatibility. These pins must be used to send DC signals only during the blanking time. When ISEL/RST# = LOW, DKEN = HIGH DK[3:1] are active, these inputs are used to select the De-skewing setting for the input bus. When ISEL/RST# = HIGH, DKEN = HIGH 2 A[3:1] are active, these bits are used to set the lower 3 bits of the I C device address.
D[11:0]
5055, 58-63 57 56
In
IDCK+ IDCK-
In In
DE HSYNC VSYNC CTL1/A1/DK1 CTL2/A2/DK2 CTL3/A3/DK3
2 4 5 8 7 6
In In In In
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SiI 164 PanelLink Transmitter Data Sheet
Pin Descriptions (cont'd)
Configuration Pins
Pin Name Pin #
MSEN 11
Type
Out
Description
Monitor Sense. This pin is an open collector output. The behavior of this output depends on 2 whether I C interface active: 2 I C bus inactive (ISEL/RST# = LOW) HIGH level indicates a powered on receiver is detected at the differential outputs. A LOW level indicates a powered on receiver is not detected. 2 I C bus is enabled (ISEL/RST# = HIGH) 2 2 The output is programmable through the I C interface (see I C Register Definitions). An external 5K pull-up resistor to VDDQ is required on this pin. 2 I C Interface Select. ISEL/RST#=HIGH, 2 I C interface is active. ISEL/RST#=LOW, 2 I C is inactive and the chip configuration is read from the configuration strapping pins. This pin 2 also acts as an asynchronous reset to the I C interface controller. The reset is active when this input is held LOW. 2 Note: When the I C interface is active, DKEN must be set HIGH. 2 2 Input bus select / I C clock. This pin is an open collector input. If I C bus is enabled 2 2 (ISEL/RST# = HIGH), then this pin is the I C clock input. If the I C is disabled (ISEL/RST# = LOW), then this pin selects the input bus width. Input Bus Select: HIGH selects 24-bit input mode LOW selects 12-bit input mode 2 2 Dual edge clock select / I C Data. This pin is an open collector input/output. If I C bus is 2 2 enabled (ISEL/RST# = HIGH), then this pin is the I C data line. If the I C bus is disabled (ISEL/RST# = LOW), then this pin selects whether single clock dual edge is used. Dual Edge clock select: When HIGH, IDCK+ latches input data on both falling and rising clock edges. When LOW, IDCK+/IDCK- latches input data on only falling or rising clock edges. In 24-/12-bit mode: If HIGH (dual edge), IDCK+ is used to latch data on both falling and rising edges. st nd If LOW (single edge), IDCK+ latches 1 half data and IDCK- latches 2 half data. 2 Edge select / Hot Plug input. If the I C bus is enabled (ISEL/RST# = HIGH), then this pin is TM (R) TM used to monitor the "Hot Plug" detect signal (Please refer to the DVI or VESA P&D and DFP standards). This Input is ONLY 3.3V tolerant and has no internal de-bouncer circuit. 2 If I C bus is disabled (ISEL/RST# = LOW), then this pin selects the clock edge that will latch the data. How the EDGE setting works depends on whether dual or single edge latching is selected: Dual Edge Mode (DSEL = HIGH) EDGE = LOW, the primary edge (first latch edge after DE is asserted) is the falling edge. EDGE = HIGH, the primary edge (first latch edge after DE is asserted) is the rising edge. Note: In 24-bit Single Clock Dual Edge mode, EDGE is ignored. Single Edge Mode (DSEL = LOW) EDGE = LOW, the falling edge of the clock is used to latch data. EDGE = HIGH, the rising edge of the clock is used to latch data. De-skewing enable. 2 I C mode (ISEL/RST# = HIGH) DKEN pin must be set to HIGH. DK[3:1] pins are ignored and the De-skewing increments are 2 2 selected through the I C interface (see the I C register definitions). 2 Non I C mode (ISEL/RST# = LOW) DKEN = LOW, then default De-skewing setting is used. DKEN = HIGH, then DK[3:1] is used as the De-skewing setting. The De-skewing increments are TSTEP. Please see Data De-skew Feature for an illustration.
ISEL/RST#
13
In
BSEL/SCL
15
In
DSEL/SDA
14
In/Out
EDGE/ HTPLG
9
In
DKEN
35
In
9
SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Pin Descriptions (cont'd)
Input Voltage Reference Pin
Pin Name Pin # Type
VREF 3 Analog In
Description
Input Reference Voltage. Selects the Swing range of the digital inputs, which include only D[23:0], IDCK+, IDCK-, DE, VSYNC, and HSYNC. Input pins SCL and SDA, RST, BSEL, DSEL, EDGE and PD# require 3.3V high swing signals and are not changed by the VREF input. To set the digital inputs to 3.3V High Voltage Swing, VREF must be set to 3.3V. To set the digital inputs to Low Voltage Swing, VREF must be set to 1/2 of VDDQ where VDDQ is swing level of input signal. Thus for DVO mode(1.5V Low Voltage Swing) VREF should be set to 0.75V and BSEL=LOW.
Power Management Pins
Pin Name Pin #
PD# 26
Type
In
Description
Power Down (active LOW). A HIGH level indicates normal operation. A LOW level indicates Power Down mode. In Power Down mode the Analog core is disabled and Output 2 buffers/pins are tri-stated however the Input buffer/pins and I C Block for read and write are 2 2 active. PD# pin is disabled during I C mode. PD# should be tied low during I C mode.
Differential Signal Data Pins
Pin Name
TX0+ TX0TX1+ TX1TX2+ TX2TXC+ TXCEXT_SWING
Pin #
25 24 28 27 31 30 22 21 19
Type
Analog Analog Analog Analog Analog Analog Analog Analog Analog
Description
TMDS Low Voltage Differential Signal input data pairs. These pins are tri-stated when PD# is pulled low.
TMDS Low Voltage Differential Signal input clock pair. These pins are tri-stated when PD# is pulled low. Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor sets the amplitude of the voltage swing. A smaller resistor value sets a larger voltage swing and vice versa. For remote display applications a 510 resistor is recommended. While for notebook computers 680 is recommended to ensure voltage swing is not overdriven over a short cable distance.
Reserved Pins
Pin Name
RESERVED
Pin # Type Description
34 In Must be tied LOW for normal operation.
Power and Ground Pins
Pin Name
VCC GND AVCC AGND PVCC1 PVCC2 PGND
Pin #
1,12,33 16,48,64 23,29 20,26,32 18 49 17
Type
Power Ground Power Ground Power Power Ground
Description
Digital VCC, must be set to 3.3V nominal. Digital GND. Analog VCC, must be set to 3.3V nominal. Analog GND. Primary PLL Analog VCC, must be set to 3.3V nominal. Filter PLL Analog VCC, must be set to 3.3V nominal. PLL Analog GND.
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SiI 164 PanelLink Transmitter Data Sheet
I2C Registers
I C Register Mapping
Addr. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 7 0x0C Bit 7 Bit 6 Bit 3 VND_IDL (RO) VND_IDH (RO) DEV_IDL (RO) DEV_IDH (RO) DEV_REV (RO) RSVD[7:0] FRQ_LOW (RO) FRQ_HIGH (RO) VEN HEN DSEL (RW) (R/W) (R/W) MSEL[2:0] (RW) TSEL (RW) DKEN (RW) 4 CFG[7:0] (RO) RSVD Bit 5 Bit 4 Bit 2 Bit 1 Bit 0
2
RSVD[1:0] VLOW (RO)
BSEL (RW) RSEN (RO) CTL[3:1] (RW)
EDGE (RW) HTPLG (RO)
PD (RW) MDI (RW) RSVD PFEN (RW)
DK[3:1] (RW) SCNT (RW)
0x0D RSVD[3:0] 0x0E RSVD[7:0] 0x0F RSVD[7:0] Notes 1. All values are Bit 7(MSB) and Bit 0(LSB). 2. Registers that can be written and read from are listed as (R/W) while registers that can be read only are listed with (RO). 3. Actual jitter tolerance may be higher depending on the frequency of the jitter. 4. Contents of this register are dependent on the status of pins D[23:16]. 2 5. After the RESET signal is deasserted in I C mode, only PD and MSEL have a default value or can retain their programmed value set before the reset. All other registers do not have a default value or retain their value after a reset. 2 As such all required registers other than PD and MSEL must reinitialized in I C mode after being powered up or reset. 6. Registers listed as RSVD are reserved and for Silicon Image, Inc use only. 7. 0x0C is also called the VDJK Register. Default setting for the VDJK register 0x0C is 89h, which is optimum for most applications.
PLLF[3:1] (RW) RSVD[3:0]
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SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
I C Register Definitions
Register Name VND_IDL VND_IDH DEV_IDL DEV_IDH DEV_REV FRQ_LOW FRQ_HIGH PD Access RO RO RO RO RO RO RO RW Description Vendor ID Low byte (01h) Vendor ID High byte (00h) Device ID Low byte (06h) Device ID High byte (00h) Device Revision (00h) Low frequency limit at 1-pixel/clock mode (MHz) (19h) High frequency limit at 1-pixel/clock mode Max frequency minus 65MHz (MHz) (64h) Power Down mode (same function as PD# pin) 0 - Power Down (Default after RESET) 1 - Normal operation Edge Select (same function as EDGE pin) 0 - Input data is falling edge latched (falling edge latched first in dual edge mode) 1 - Input data is rising edge latched (rising edge latched first in dual edge mode) Input Bus Select (same function as BSEL pin) 0 - Input data bus is 12-bits wide 1 - Input data bus is 24-bits wide Dual Edge Clock Select (same function as DSEL pin) 0 - Input data is single edge latched 1 - Input data is dual edge latched Horizontal Sync Enable: 0 - HSYNC input is transmitted as fixed LOW 1 - HSYNC input is transmitted as is Vertical Sync Enable: 0 - VSYNC input is transmitted as fixed LOW 1 - VSYNC input is transmitted as is Monitor Detect Interrupt 0 - Detection signal has changed logic level (write one to this bit to clear) 1 - Detection signal has not changed state Hot Plug Detect input, the state of HTPLG pin can be read from this bit Receiver Sense (only available for use in DC coupled systems) 0 - Active/Powered Receiver not detected 1 - Active/Powered Receiver detected Interrupt Generation Method 0 - Interrupt bit (MDI) is generated by monitoring RSEN 1 - Interrupt bit (MDI) is generated by monitoring HTPLG Select source of the MSEN output pin 000 - Force MSEN outputs high (disabled - default after RESET) 001 - Outputs the MDI bit (interrupt) 010 - Output the RSEN bit (receiver detect) 011 - Outputs the HTPLG bit (hot plug detect) 1xx - RESERVED This bit is a 1 if the VREF setting 1 - Indicates High Swing inputs 0 - Indicates Low Swing inputs General purpose inputs (same as CTL[3:1] pins)
2
EDGE
RW
BSEL
RW
DSEL
RW
HEN
RW
VEN
RW
MDI
RW
HTPLG RSEN
RO RO
TSEL
RW
MSEL[2:0]
RW
VLOW
RO
CTL[3:1]
RW
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SiI 164 PanelLink Transmitter Data Sheet
I C Register Definitions (cont'd)
Register Name
CFG[7:0] PFEN
2
Access
RO RW
Description
Contains state of inputs D[23:16]. These pins can be used to provide user selectable 2 configuration data through the I C bus. Only available in 12-bit mode PLL Filter Enable in the VDJK Register. 1 - To enable PLL Filter (recommended setting) 0 - To disable PLL Filter Set characteristics of PLL filter in the VDJK register 100 - Recommended value SYNC Continuous 1 - To enable (recommended setting) 0 - To disable De-skewing Setting. Increment 260psec. 000 - 1 step -> minimum setup / maximum hold 001 - 2 step 010 - 3 step 011 - 4 step 100 - 5 step -> default (recommended setting) 101 - 6 step 110 - 7 step 111 - 8 step -> maximum setup / minimum hold Please see Data De-Skew Feature for an illustration De-skewing Enable through DK[3:1] bits. When DKEN pin is HIGH via pin or set to 1, then De-skew is enabled. When set to 0 De-skew is disabled. Please see Data Deskew Feature for an illustration.
PLLF[3:1] SCNT
RW RW
DK[3:1]
RW
DKEN
RW
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SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet I C Slave Interface and Address The SiI 164 slave state machine does not require an internal clock and support only byte read and write. Page 2 mode is not supported. The 7-bit binary address of the I C machine is "0111 A3A2A1R" where R =1 sets a read operation while R=0 sets a write operation. Please see Figure 10 for a Byte Read operation and Figure 11 for a byte 2 2 write operation. For more detailed information on I C protocols please refer to I C Bus Specification version 2.1 available from Philips Semiconductors Inc. When ISEL/RST# = HIGH and DKEN = HIGH, pins 6,7,8 functions as A[3:1]. Each pin can be set to HIGH or LOW 2 to select a desired I C address for the SiI 164. To set the SiI 164 to 72h, tie pin 7 and 6 to ground and pull pin 8 to VCC via 2.2K resistor. The recommended setting is to tie pins 6,7 and 8 to ground to set "000" or address 70h in 2 I C mode .
Slave Address Slave Address
2
Start
Start
Register Address
SDA Line
S
AAA 321 A C K
2
S A C K
AAA 321 A C K
Bus Activity : SiI 164
Data
Figure 10. I C Byte Read
Start
Address
Data
SDA Line
S
AAA 321 A C K A C K
2
Bus Activity : SiI 164
A C K
Figure 11. I C Byte Write
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Stop
Bus Activity : Master
Slave Address
P
Stop P
Bus Activity : Master
SiI 164 PanelLink Transmitter Data Sheet
Data De-skew Feature
Input clock to data setup/hold time can be adjusted through the use of the De-skew feature. It should be noted that 2 it is the clock that is being adjusted. When DKEN is HIGH, the configuration pins DK[3:1] or applicable I C register bits (DK[3:1]) can be used to vary the input setup/hold time by an amount TCD given by the formula TCD = (DK[3:1] - 4) x TSTEP. Where: TCD is the amount of setup/hold timing variation 2 DK[3:1] is the setting of the de-skew configuration pins or I C registers This feature can be used in 12-bit or 24-bit mode. If DKEN is set LOW and the SiI 164 is not in I C mode, the DK[3:1] inputs are ignored, and the default setting of TCD = 0 is used.
2
D [23:0], DE, VSYNC, HSYNC, C T L [3:1] CLK+
CLK-T C D D K [3:1] 000
d efau lt
T CD 100 111
Figure 12. SiI 164 Data De-skew Feature Timing
15
SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Data Latching Modes
SiI 164 can be set to different to operate in either 12 bit or 24 bit input mode. In either mode the SiI 164 can be set to latch data at either rising or falling edge of the clock or support dual edge clocking mode. Figure 13 illustrates the latching edge for a 12 bit data input (BSEL = 0) by changing DSEL and EDGE option. Clock edges represented by arrows signify the latching edge. For Dual Edge mode, the dark arrows indicate the primary latch edge.
DE
L = Low half pixel H = High half pixel
D[11:0]
P 0L
PO H
P 1L
P 1H
PN-1H
PN L
P NH
IDCK+
DSEL = 1
IDCK+
DSEL = 0
EDGE = 0
IDCK-
IDCK+
DSEL = 1
IDCK+
DSEL = 0
EDGE = 1
IDCKFirst Latch Edge
Figure 13. 12 bit Input Data Latching Figure 14 illustrates the latching edge for a 24 bit data input (BSEL=1) with DSEL and EDGE option. EDGE pin has no affect in 24-bit Single Clock Dual Edge Mode.
DE
D[23:0]
P0
P1
PN-1
PN
IDCK+
DSEL = 1, EDGE = 0
IDCK+
DSEL = 0, EDGE = 0
IDCK+
DSEL = 1, EDGE = 1
IDCK+
DSEL =0, EDGE = 1
First Latching Edge
Figure 14. 24 bit Input Data Latching
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SiI 164 PanelLink Transmitter Data Sheet
I C Programming Sequence
To program the SiI 164 in data latched on 12 bit mode Dual Edge Clock with Primary Edge as the rising edge, Deskew enabled without Hotplug and the following sample programming sequence listed in Table 1 may be used. It is 2 important to note that the suggested I C address for SiI 164 be set to x70h by tying A1, A2 and A3 to ground. Table 1. Sample Programming Sequence for SiI 164
Register(Hex) 0x08 0x09 0x0A 0x0C 0x08 Value(Hex) 31 00 90 89 33 Description st Enable HEN, VEN, 1 data latched on rising edge with PD low until all registers are programmed. MSEN disabled. De-skew enabled with default 100 value. CTL is not used. SCNT, PLL Filter Enable and PLL Bandwidth Filter set to default. Set PD to High after the registers above have been programmed.
2
Enabling Hot Plug Detection Mode
As documented in the VESA Digital Flat Panel Standard, all monitors are required to support Hot Plug Detection 2 but support is optional for the host. The SiI 164 supports the Hot Plug Detect feature. In I C mode, pin 9 functions as HTPLG input. It should be noted that the HTPLG pin on the SiI 164 is only 3.3V tolerant therefore HTPLG voltage level from the DVI connector should be level shifted or clamped at 3.3V. When the voltage level at the HTPLG pin is 3.3V, the HTPLG bit will be set to 1. To output the HTPLG bit via the MSEN pin, register MSEL[2:0] should be programmed to 011. The SiI 164 can also be programmed to enable the Hot Plug Detection Mode via the Receiver Sense function. In this mode, HTPLG pin is not required. By programming MSEL[2:0] to 010, SiI 164 will output the RSEN=1 bit though the MSEN pin when the SiI 164 is connected to a powered receiver.
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SiI 164 PanelLink Transmitter Data Sheet
Non I C Mode Configuration
The SiI 164 can be set to program itself at power up without writing any SiI 164 registers via I C. The SiI 164 is 2 2 extremely flexible and can be set to operate in any input format that can be set in I C mode. In non I C mode, specific configuration pins need to be strapped to either high or low to set the desired mode. Figure 15 provides a 2 schematic example of all the pins that can be configured to enable the various modes in non I C mode. Table 2 lists resistors to be stuffed for a specific mode.
AVCC R16 510 1% 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 58 59 60 61 62 63 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 19 3.3V R7 R8 R9 R10 R11
2
2
A
EXT_RES
C
PD DKEN DK1 DK2 DK3
10 35 8 7 6
PD DKEN DK1 DK2 DK3
33K 33K 33K 33K 33K R12 R13 R14 R15 330 0 0 0
D[11..0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ISEL/RST RSVD
13 34
B
3.3V R1 2.2K R4 R5 R6 330 330 330 R2 2.2K BSEL DSEL EDGE R3 2.2K 15 14 9
3.3V BSEL/SCL DSEL/SDA EDGE/CHG/SIN Sil 164 R17 3 VREF 2.2K
1.5V or VDDQ
D
R18 15K
VREF
R19 15K
Figure 15. Non I C Mode Schematic Example
2
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SiI 164 PanelLink Transmitter Data Sheet
Non I C Mode Configuration (cont'd)
ISEL/RST# and RSVD pins must always be tied to ground for non I C mode. PD# must be tied high or the SiI 164 will still be in Power Down mode when VCC is applied. In Figure 15 Block A corresponds to the upper 12 bits (D [23:12]) of the SiI 164. When not in use, they should always be tied to ground. Block B controls the Input Bus data width, Dual Edge Clock Select and Edge Select. IDCK- is only used in 12 bit mode. In 24 bit mode or Dual Edge Clock select IDCK- should be tied to ground. Block C controls the De-skew options. Block D determines the input voltage level swing. A full description of each pin can be found in the Pin Description section of this document. Table 2. Non I C Strapping Mode Options
MODE 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 24 bit Single Clock Dual Edge Falling Edge st latching 1 pixel De-skewing enabled to 100 High Voltage Swing 24 bit Single Clock Single Edge Falling Edge De-skewing disabled High Voltage Swing. 12 bit Single Clock Dual Edge Rising Edge of st IDCK+ latching 1 1/2 pixel De-skewing disabled High Voltage Swing. 12 bit Dual Clock Dual Edge, Falling Edge of st IDCK+ latching 1 1/2 pixel De-skewing enabled to 100 Low Swing Mode
3 2 1
2
2
2
BLOCK A
BLOCK B
BLOCK C
BLOCK D
Connect D[23:12] to VGA Source
Stuff only R1, R2, R6
Stuff only R8, R13, R14, R11
Stuff Only R17
Connect D[23:12] to VGA Source
Stuff only R1, R5, R6
Stuff only R12, R13, R14, R15
Stuff Only R17
Ground D[23:12]
Stuff only R4, R2, R3
Stuff only R12, R13, R14, R15
Stuff Only R17
5. 6. 1. 2. 3. 4. 5. 6.
Ground D[23:12]
Stuff only R4, R5, R6
Stuff only R8, R13, R14, R11
Stuff Only R18, R19
Notes 1. In 24 bit IDCK+ is input clock. IDCK- should be tied to ground. 2. In 12 bit dual edge mode, IDCK- is not used. 3. This setting is equivalent to DVO mode. In DVO mode both IDCK+ and IDCK- must be connected.
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SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
TFT Panel Data Mapping
The following TFT data mapping tables are strictly listed for single link TFT applications only. SiI 143B, SiI 151B, SiI 153B and SiI 161B all have the same pinout. As such mapping will be the same when SiI 143B or SiI151B or SiI153B is used in place of SiI 161B. Table 3. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2
TFT VGA Output 24-bpp 18-bpp B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 Shift CLK VSYNC HSYNC DE Tx Input Data 160 164 DIE0 DIE1 DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 DIE8 DIE9 DIE10 DIE11 DIE12 DIE13 DIE14 DIE15 DIE16 DIE17 DIE18 DIE19 DIE20 DIE21 DIE22 DIE23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 Rx Output Data 161B 141B QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23
TM
Compliant
TFT Panel Input 24-bpp 18-bpp B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7
B0 B1 B2 B3 B4 B5
B0 B1 B2 B3 B4 B5
G0 G1 G2 G3 G4 G5
G0 G1 G2 G3 G4 G5
R0 R1 R2 R3 R4 R5
R0 R1 R2 R3 R4 R5
Shift CLK IDCK IDCK ODCK ODCK Shift CLK Shift CLK VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC DE DE DE DE DE DE DE
For 18-bit mode, the Flat Panel Graphics Controller interfaces to the transmitter exactly the same as in the 24-bit mode; however, 6 bits per channel (color) are used instead of 8. It is recommended that unused data bits be tied low. As can be seen from the above table, the data mapping for less than 24-bit per pixel interfaces are MSB justified. The data is sent during active display time while the control signals are sent during blank time. Note that the three data channels (CH0, CH1, CH2) are mapped to Blue, Green and Red data respectively.
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SiI 164 PanelLink Transmitter Data Sheet Table 4. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode
TFT VGA Output 24-bpp B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 Tx Input Data 160 164 DIE0 D0 DIE1 D1 DIE2 D2 DIE3 D3 DIE4 D4 DIE5 D5 DIE6 D6 DIE7 D7 DIE8 D8 DIE9 D9 DIE10 D10 DIE11 D11 DIE12 D12 DIE13 D13 DIE14 D14 DIE15 D15 DIE16 D16 DIE17 D17 DIE18 D18 DIE19 D19 DIE20 D20 DIE21 D21 DIE22 D22 DIE23 D23 Rx Output Data 161B QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QO0 QO1 QO2 QO3 QO4 QO5 QO6 QO7 QO8 QO9 QO10 QO11 QO12 QO13 QO14 QO15 QO16 QO17 QO18 QO19 QO20 QO21 QO22 QO23 ODCK VSYNC HSYNC DE TFT Panel Input 24-bpp B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 B6 - 0 B7 - 0 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 G6 - 0 G7 - 0 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 R6 - 0 R7 - 0 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 B6 - 1 B7 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 G6 - 1 G7 - 1 R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 R6 - 1 R7 - 1 Shift CLK/2 VSYNC HSYNC DE
Shift CLK VSYNC HSYNC DE
IDCK VSYNC HSYNC DE
IDCK VSYNC HSYNC DE
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SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet Table 5. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode
TFT VGA Output 18-bpp Tx Input Data 160 164 DIE0 D0 DIE1 D1 DIE2 D2 DIE3 D3 DIE4 D4 DIE5 D5 DIE6 D6 DIE7 D7 DIE8 D8 DIE9 D9 DIE10 D10 DIE11 D11 DIE12 D12 DIE13 D13 DIE14 D14 DIE15 D15 DIE16 D16 DIE17 D17 DIE18 D18 DIE19 D19 DIE20 D20 DIE21 D21 DIE22 D22 DIE23 D23 Tx Output Data 161B 141B QE0 QE1 QE2 Q0 QE3 Q1 QE4 Q2 QE5 Q3 QE6 Q4 QE7 Q5 QE8 QE9 QE10 Q6 QE11 Q7 QE12 Q8 QE13 Q9 QE14 Q10 QE15 Q11 QE16 QE17 QE18 Q12 QE19 Q13 QE20 Q14 QE21 Q15 QE22 Q16 QE23 Q17 QO0 QO1 QO2 Q18 QO3 Q19 QO4 Q20 QO5 Q21 QO6 Q22 QO7 Q23 QO8 QO9 QO10 Q24 QO11 Q25 QO12 Q26 QO13 Q27 QO14 Q28 QO15 Q29 QO16 QO17 QO18 Q30 QO19 Q31 QO20 Q32 QO21 Q33 QO22 Q34 QO23 Q35 ODCK Shift CLK/2 VSYNC VSYNC HSYNC HSYNC DE DE TFT Panel Input 18-bpp
B0 B1 B2 B3 B4 B5
B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0
G0 G1 G2 G3 G4 G5
G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0
R0 R1 R2 R3 R4 R5
R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0
B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1
G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1
Shift CLK VSYNC HSYNC DE
IDCK VSYNC HSYNC DE
IDCK VSYNC HSYNC DE
R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 Shift CLK/2 VSYNC HSYNC DE
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SiI 164 PanelLink Transmitter Data Sheet
Design Recommendations
1.5V to 3.3V I C Bus Level-Shifting
To program the SiI 164 via I C mode SDA and SCL swing level must be 3.3V. DVO sources have I C swing of 1.5V. To ensure proper initialization of the SiI 164 a bi-directional voltage level-shifting circuit between the SiI 164 2 I C bus and the VGA or driving source should be implemented. Two suggested components that can be used to achieve this is by using either a dual N-channel transistor like Fairchild Semiconductor's NDC7002N or the Philips GTL2010 High Speed Bus Switch. Refer to Figure 16 for a schematic example using a dual N-channel transistor 2 2 for translating an I C 1.5V signal to 3.3V I C signal and vice versa.
1.5V 2.9V 1 3.3V
2 2
2
1K
Q2 G D3 2N7002 3.3V
2.2K 3.3V I2C DATA TO SiI 164
1.5V I2C DATA FROM VGA 1.5V
2S 2.9V 1
1K
Q4 G D3 2N7002
2.2K 3.3V I2C CLK TO SiI 164
1.5V I2C CLK FROM VGA
2S
Figure 16. I C Bus Voltage Level-Shifting using Fairchild NDC7002N
2
Figure 17 illustrates a schematic example using the Philips GTL 2010 to achieve a 1.5V to 3.3V bi-directional level-shift.
1.5V
5V R2 1K
3.3V
R1 1K
R3 200K U1 1 2 3 4 5 6 7 8 9 10 11 12 GND GREF SREF DREF S1 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8 D8 S9 D9 S10 D10 GTL2010 24 23 22 21 20 19 18 17 16 15 14 13
R4 2.2K
R5 2.2K 3.3V I2C DATA TO SiI 164 3.3V I2C CLK TO SiI 164
1.5V I2C DATA FROM VGA 1.5V I2C CLK FROM VGA
Figure 17. I C Bus Voltage Level Shifting using Philips GTL 2010
2
23
SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Voltage Ripple Regulation
The power supply to PVCC is very important to the proper operation of the Transmitter chips. PVCC does not draw much current so any voltage regulator that can supply 50mA or more is sufficient. Two suggested voltage regulators are TL431 from Texas Instruments or LM317 from National Semiconductor. Two examples are shown in Figure 18 and Figure 19
100-150 ohms Vin (5V) 1K ohms 1% Vref 3K ohms 1% Ref Cathode TL431 Anode
Vout (3.3V) to PVCC1 and PVCC2
Figure 18. Voltage Regulation using TL431
Decoupling and bypass capacitors are also involved with power supply connections, as described in detail in Figure 20 and Figure 21.
LM317EMP Vout (3.3V) to PVCC1 and PVCC2 240 ohms
Vin (5V)
VIN
VOUT ADJ
390 ohms
Figure 19. Voltage Regulation using LM317
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SiI 164 PanelLink Transmitter Data Sheet
Decoupling Capacitors
Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown schematically in Figure 21. Place these components as closely as possible to the SiI 164 pins, and avoid routing through vias if possible, as shown in Figure 20, which is representative of the various types of power pins on the transmitter.
VCC C1 C2 L1 Ferrite
VCC
GND
Via to GND
C3
Figure 20. Decoupling and Bypass Capacitor Placement
VCC
L1 VCCPIN C1 C2 C3
Figure 21. Decoupling and Bypass Schematic
The values shown in Table 6 are recommendations that should be adjusted according to the noise characteristics of the specific board-level design. Pins in one group (such as VCC) may share C2, L1, and C3, each pin having C1 placed as closely to the pin as possible. Table 6. Recommended Components for Bypass and Decoupling Circuits
C1 100 - 300 pF C2 2.2 - 10 F C3 10 F L1 200+
25
SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Series Damping Resistors on Outputs
Series resistors are effective in lowering the data-related emissions and reducing reflections. Series resistors with suggested value of 22 or 33 should be placed close to the output pins of the VGA Source or Graphics chip, as shown in Figure 22.
D[23..0]
VGA
Figure 22. Series Input Damping Resistors for Driving Source
Differential Trace Routing
The routing for the SiI 164 chip is relatively simple since no spiral skew compensation is needed. However, a few small precautions are required to achieve the full performance and reliability of DVI. The Transmitter can be placed fairly far from the output connector, but care should be taken to route each differential signal pair together and achieve impedance of 100 between the differential signal pair. However, note that the longer the differential traces are between the transmitter and the output connector, the higher the chance that external signal noise will couple onto the low-voltage signals and affect image quality. Do not split or have asymmetric trace routing between the differential signal pair. Vias are very inductive and can cause phase delay problems if applied unevenly within a differential pair. Vias should be minimized or avoided if possible by placing all differential traces on the top layer of the PCB. Figure 23 illustrates an incorrect routing of the differential signal from the SiI 164 to the DVI connector. Figure 24 illustrates the correct method to route the differential signal from the SiI 164 to the DVI connector. Figure 25 illustrates recommended routing for differential traces at the DVI connector.
TX
Figure 23. Example of Incorrect Differential Signal Routing
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26
SiI 164 PanelLink Transmitter Data Sheet
TX
Figure 24. Example of Correct Differential Signal Routing
24 16 8
17 9 1
TxCTxC+
Figure 25. Differential Trace Routing to DVI Connector(Top Side View)
Tx2Tx2+
Tx1Tx1+
Tx0Tx0+
27
SiI-DS-0021-C
SiI 164 PanelLink Transmitter Data Sheet
Package Dimensions
Lead Length 1.00mm
Lead Width 0.22mm
64-pin Plastic TQFP
Lead Pitch 0.50mm Body Size 10.00mm Footprint 12.00mm
Device # Lot # Date Code SiI Rev. #
SII164CT64 LNNNNN.NLLL YYWW X.XX
Package Height 1.15mm max.
Clearance 0.15mm max.
Body Thickness 1.0 mm Body Size 10.00mm Footprint 12.00mm
Figure 26. 64-pin TQFP Package Dimensions (JEDEC code MS-026ED)
Ordering Information
Part Number: SII164CT64
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SiI 164 PanelLink Transmitter Data Sheet
(c) 2002 Silicon Image. Inc. 04/02 SiI-DS-0021-C Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 USA Tel: Fax: E-mail: Web: (408) 616-4000 (408) 830-9530 salessupport@SiImage.com www.siliconimage.com 29 SiI-DS-0021-C

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